High-capacitance, on-chip capacitors are widely used in various types of digital and analog ICs such as dynamic random access memory (DRAM) and phase-lock loop (PLL), etc. Traditionally, such a capacitor comprises two sets of parallel metal wires embedded in different dielectric layers above a semiconductor substrate, each set being connected to one of the two terminals of the capacitor. The capacitance of the capacitor is a function of the number of metal wires connected to one terminal, their respective length, width, and distance to neighboring metal wires connected to the other terminal. For example, a capacitor having longer metal wires usually has a higher capacitance provided that other geometric parameters remain the same.
Several shortcomings have been attributed to the aforementioned design of a capacitor structure. First, it is not flexible. Each specific design is associated with a fixed capacitance. If an IC requires a capacitance different from an existing design, a circuit designer has to compute a different set of geometric parameters for a new capacitor structure that will provide the required capacitance. As a result, the IC manufacturing process has to be modified to fabricate the new capacitor structure. If an IC needs multiple on-chip capacitors, each having a unique capacitance, this could significantly increase the cost of IC design and manufacturing. Second, a capacitor comprised of longer metal wires is often accompanied by serious side effects. Such a capacitor tends to have higher parasitic resistance and inductance. This reduces the efficiency of the capacitor, especially at higher frequencies.
In view of the aforementioned issues, there is a need for an on-chip capacitor structure that is flexible to satisfy different capacitance requirements. It is also desirable that the capacitor structure have a better performance than the conventional on-chip capacitors in the domain of high operating frequencies.